The present invention relates to a semiconductor memory comprising means for substituting a spare memory block for a normal memory block when the latter is found defective, so as to deal with the defect. More particularly, the present invention relates to a semiconductor memory which can also be used as a general-purpose memory and which is suitable to efficiently deal with or repair a defect or failure as described above.
Redundancy techniques are widely used as an effective means for improving the yield rate of and reducing the manufacturing costs of semiconductor memories. These techniques are described in, for example, the following papers:
(1) ISSCC, Digest of Technical Papers, pp. 80-81, February 1981; PA1 (2) IEEE, Journal of Solid-State Circuits, Vol. SC-15, No. 4, pp. 677-686, August 1981; and PA1 (3) ISSCC, Digest of Technical Papers, pp. 240-241, February 1989.
The redundancy technique described in the paper (1) is now most usually used for semiconductor memories. That is, a spare word line or a spare bit line provided beforehand on the chip of a semiconductor memory is used to substitute a word line or a bit line including a defective memory cell. On the other hand, the paper (2) proposes to use a larger block unit for substitution. That is, this paper relates to the so-called full-wafer scale integration in which an entire wafer is integrated into a single memory. The paper (3) relates also to the full-wafer scale integration. However, according to the proposed method therein, a defective memory cell is not targeted for substitution, and the memory system which is composed on the wafer isolates such a defective memory chip on the wafer.
One of the problems of the prior art redundancy techniques described above is that it is unable to remedy a failure (referred to hereinafter as a DC failure) where the chip consumes an excessively large current, especially in the stand-by mode. Because a chip where the stand-by current is larger than a specified value must be discarded as a reject, this DC failure is a great obstacle for the desired improvement in the yield rate of semiconductor memories. This DC failure is attributable to various causes, and that which will occur in a memory array of, for example, a DRAM will be described now with reference to FIG. 11.
FIG. 11 is an equivalent circuit diagram of a memory array and a sense circuit of a DRAM using conventional memory cells of one transistor/one capacitor type. Memory cells MC are arrayed at the intersections of word lines W and data line pairs D and D. P designates a plate (an opposite electrode of the capacitor in each memory cell). A sense circuit 11 includes a sense amplifier 110 amplifying a signal voltage on the data lines and a precharge circuit 111 used for initially setting the data line potential. The potential at each node is as follows when this memory is in its stand-by mode. First, all of the word lines W are not selected, and their potential is fixed at the ground potential (OV). The data lines D and D are connected to a source of a DC voltage V.sub.MP through the precharge circuit 111 and a power supply line 115. The plate P is connected to a source of a DC voltage V.sub.PL by a power supply line 105. In a modern DRAM, the values of the DC voltages V.sub.MP and V.sub.PL are usually selected to be 1/2 of the power supply voltage V.sub.cc.
Suppose now that a short-circuit occurs between the word line W and the data line D as shown at 108. Because of such a defect, the current from the voltage source V.sub.MP (=V.sub.cc /2) flows to the ground through the precharge circuit 111, the data line D and the word line W. On the other hand, when a short-circuit occurs between the word line Wi and the plate P as shown at 109, the current from the voltage source V.sub.PL (=V.sub.cc /2) flows to the ground through the plate P and the word line Wi. In each of these cases, an excessively large direct current flows in the stand-by mode. These failures cannot be remedied by the prior art redundancy techniques. This is because, even when the defective word and data lines W and D are substituted by a spare word line and a spare data line respectively so that they may not be selected, the current paths described above still remain in the memory placed in the stand-by mode.
The paper (3) cited above proposes to turn off the power supply switch for such a defective chip. It is true that the DC failure can be remedied by turning off the power supply switch. However, the method proposed in the paper (3) has the problems which will be described now. Firstly, a ROM for storing the position of such a defective chip is additionally required as an external circuit of the wafer. Secondly, because the defective memory chip is isolated, the usable capacity of the memory is not fixed and is dependent on the number and distribution of the defective chips. For these reasons, the proposed method is not applicable to fabrication of general-purpose memories such as DRAMs and SRAMs, and its application is limited. Also, the control circuit requires a large circuit scale (resulting in about a 20% increase in the chip area), and increased power consumption is also required.